The present invention relates to a semiconductor memory having dynamic memory cells, and more particularly to improved control for refresh operation of such semiconductor memories. The use of pseudo static RAM (hereinafter abbreviated as PS RAM) is favored nowadays because they are constructed of dynamic memory cells and static peripheral circuits and have the advantages of both.
Conventional refresh operation for a dynamic memory cell such as a PS RAM includes the three types of operation of chip-only refresh, auto refresh and self refresh. According to chip-only refresh operation, a refresh address is supplied to a memory externally to effect dummy access and then refresh operation. According to auto refresh operation, a refresh address counter is incorporated into a RAM to supply to its refresh terminal a refresh request signal clocked externally as shown in the timing chart of FIG. 1, to thus effect refresh operation each time the refresh request signal is input. The refresh period is determined in accordance with the period of the refresh request signals. According to self refresh operation, a refresh address counter and timer are included in the RAM to drive the timer while maintaining the external refresh request signal at the low (L) level as shown in the timing chart of FIG. 2, to therefore effect refresh operation for each carry-over cycle of the timer. The refresh cycle is determined in accordance with the count cycle of the internal timer counter.
An example of a computer system using PS RAM is shown in FIG. 3. In the operation of this system, by using a chip enable signal ROM-CE of, e.g., ROM 2 as a refresh request signal, auto refresh operation is performed at each operation code fetch cycle of CPU 1. During non-operation of this system, by setting the refresh request signal at the low "L" level and driving an internal timer of PS RAM 3, self refresh operation is performed. Such refresh operations are the main trend in applications.
As described above, during the operation of a conventional system using PS RAM, an auto refresh operation is performed by supplying a refresh request signal at each operation code fetch cycle. In this case, each time a refresh request signal is received, all PS RAM are refreshed as required and so a large refresh current is required. For instance, in the system shown in FIG. 3, four PS RAM are used to thus consume refresh current for four chips each time a refresh request signal is received, as shown in FIG. 4. The system power supply is accordingly required to be made large, hindering the system from being made compact and from saving energy. Furthermore, it is undesirable that the refresh current be several times as large as the operation current of PS RAMs of a large system which consumes an operation current corresponding only to 1 to 2 chips. Furthermore, although it is sufficient for ordinary PS RAM to be refreshed at a period of 16 microseconds or more, a shorter auto refresh period such as several to 1 microseconds or less is now used as the operation speed of the CPU is made high, thus consuming an unnecessarily large refresh current.
There are tradeoffs to consider, however, between a large current consumption and a simplified circuit arrangement of such a system.